The computer and the electronic industry demand of increasing its whole speed performance as well as the cost down for fabricating integrated circuits. Doubtlessly, the DRAM integrated circuits play a crucial role for a computer is concerned. A great number of DRAM memory cells are usually required, and thus they play a vital factor for determining the I/O speed of the computer. Hence, pursuing the miniaturization of the DRAM device so as to down the cost as well as high-speed performance are almost the ultimate goals.
In order to miniaturize the device, the concept of landing pad or landing plug technology is currently popular in DRAM industry so as to shrink the feature size of DRAM cell. However, the spacing between the landing pads has to be decreased so that they can provide enough areas for contact landing as the density of DRAM cells in a chip increasing to giga-bit levels. The narrower spacing will increases the fabrication difficulty due to the limitation lithography overlay. In order to achieve desired performance, the spacing need to be as small as 0.1 .mu.m for 0.21 .mu.m feature size 64M DRAM and beyond. The critical dimension of 0.1 .mu.m is quite far beyond the present technology of lithography with 248 nm DUV (deep ultra-violet) stepper or scanner. Thus the oxide spacer reduced the spacing is applied for solving the lithography limitation currently.
FIGS. 1-5 show processes for formation the landing pads according to the prior art. Referring to FIG. 1, the cross-sectional view shows a DRAM region 4 prepared for forming DRAM cells and a periphery transistors region 6 formed on a silicon substrate 2. In the DRAM region, there are two stack gates 25 with silicon nitride cap 20 and nitride spacers 17 for forming landing pads of DRAM cells. The periphery transistors region 6 includes a CMOS transistor 15A and NMOS transistors 15. The periphery transistors 15, 15A and two stack gates 25 are overlay with a LPTEOS layer (low-pressure tetraethyl orthosillicate) 28 having a thickness of about 45-55 nm. Thus, for forming the landing pads, the LPTEOS layer 28 is necessary to remove. FIG. 1 shows a result of the LPTEOS layer 28 removal in DRAM region 4 after etching using the photoresist layer 30 as a mask.
Please see FIG. 2, after the photoresist layer 30 is stripped, a doped polysilicon layer 38 is formed on all resulting surface to a thickness of about 150 nm by an in-situ doped LPCVD process. A TEOS capping layer 40 is then formed successively on the doped polysilicon layer 38 to about 90-110 nm in thickness. After that, a photoresist pattern 45 is masked on the DRAM region 4 so as to form photoresist openings 46 over each the silicon nitride cap 20. The size of opening is about 0.3 .mu.m.
Referring to FIG. 3, a TEOS etch is performed to etch unmask regions, including photoresist openings 46 and the periphery transistor region 6.
Turning to FIG. 4, a thin oxide layer 47 is formed on the resulting surfaces. The LPTEOS oxide layer 48 to a thickness of about 100 nm is generally preferred.
As shown in FIG. 5, an anisotropic etching is subsequently performed to form the oxide spacers 48 on the sidewalls of the photoresist layer 45. After that, using the spacers 48 as a mask and using the silicon nitride cap 20 as a stopping layer to etch the polysilicon layer 35 is done so that the landing pads are generated.
However, some of the oxide spacer residues 48a are formed on the sidewalls of the periphery transistors 15 and 15a, resulting in circuit short as long as the adjoining transistors are close enough. The oxide spacers 48a may cause the polysilicon layer 35 residues, which is beneath the oxide layer, left on the sidewall.
In addition, the forgoing prior is a complex method too because two oxide film deposition and twice oxide etch are required, and thus increases the cost.
Consequently, the aforementioned problems need a method to improve.